The miniaturization of semiconductors is progressing with each generation and largely relies on lithographic technology. As a result, especially in the formation of lines etc, forming a line and space pattern which has a narrower width than lithography's resolution limit is generally difficult.
To cope with this type of problem, a method is proposed whereby a sidewall pattern is formed on a dummy pattern sidewall and etching a material to be processed using this sidewall pattern as a mask is performed. This is known as (sidewall mask transfer technology). According to this method, it is possible to form a line and space pattern at a pitch of half the pitch of the dummy pattern (for example, see Japanese Patent Laid-Open Publications No. H07-263677, U.S. Pat. No. 7,112,858 and Japanese Patent Laid-Open Publications No. 2002-280388).
However, even by this method, forming precisely and effectively a line and space pattern or a whole pattern which includes another pattern is in many cases difficult. Also, for example, in the case of forming a cell gate (usually known as a word line but will be explained hereinafter referred to as a cell gate) it is pointed out that when forming a dummy pattern the pattern end becomes narrow or breaks off and there is a danger of it becoming what is called narrow open. Therefore, as miniaturization further progresses, arranging a contact with a sufficient adjustment margin on a line formed using sidewall mask transfer technology is thought to become difficult.